diff options
| author | Ayman Musa <ayman.musa@intel.com> | 2017-06-15 13:02:37 +0000 |
|---|---|---|
| committer | Ayman Musa <ayman.musa@intel.com> | 2017-06-15 13:02:37 +0000 |
| commit | 56912cda7110eeceba3c9498c2f14ac11f169a09 (patch) | |
| tree | 8f89b5b130b521d3ffbce76788927a81dad70c56 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | c70500327587e2e951433d459d62af981c649e53 (diff) | |
| download | bcm5719-llvm-56912cda7110eeceba3c9498c2f14ac11f169a09.tar.gz bcm5719-llvm-56912cda7110eeceba3c9498c2f14ac11f169a09.zip | |
[X86][AVX512] Improve lowering of AVX512 compare intrinsics (remove redundant shift left+right instructions).
AVX512 compare instructions return v*i1 types.
In cases where the number of elements in the returned value are less than 8, clang adds zeroes to get a mask of v8i1 type.
Later on it's replaced with CONCAT_VECTORS, which then is lowered to many DAG nodes including insert/extract element and shift right/left nodes.
The fact that AVX512 compare instructions put the result in a k register and zeroes all its upper bits allows us to remove the extra nodes simply by copying the result to the required register class.
When lowering, identify these cases and transform them into an INSERT_SUBVECTOR node (marked legal), then catch this pattern in instructions selection phase and transform it into one avx512 cmp instruction.
Differential Revision: https://reviews.llvm.org/D33188
llvm-svn: 305465
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
0 files changed, 0 insertions, 0 deletions
