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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-23 22:48:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-23 22:48:53 +0000 |
| commit | 4e305c6c1e0d247758eb9db13a9f9476e678e671 (patch) | |
| tree | e78773d216812f95722cae0f9f031e2f1efa719d /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | ce9d6faed6a76c907e54e2e749c726187491f138 (diff) | |
| download | bcm5719-llvm-4e305c6c1e0d247758eb9db13a9f9476e678e671.tar.gz bcm5719-llvm-4e305c6c1e0d247758eb9db13a9f9476e678e671.zip | |
DAG: Don't fold vector extract into load if target doesn't want to
Fixes turning a 32-bit scalar load into an extending vector load
for AMDGPU when dynamically indexing a vector.
llvm-svn: 292842
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index dad94c58ce9..60038e2924c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -12560,6 +12560,11 @@ SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad( if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT)) return SDValue(); + ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ? + ISD::NON_EXTLOAD : ISD::EXTLOAD; + if (!TLI.shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT)) + return SDValue(); + Align = NewAlign; SDValue NewPtr = OriginalLoad->getBasePtr(); |
