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authorCraig Topper <craig.topper@gmail.com>2016-10-14 06:00:42 +0000
committerCraig Topper <craig.topper@gmail.com>2016-10-14 06:00:42 +0000
commit40feb7f1570ab6f0d05993dc1513a9760a905c4c (patch)
treea68aaeabed153bc543d306ecae71a7a306eaf108 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parent2bd52b5d91f7f560f86eb60a7852e5c2f44aefa3 (diff)
downloadbcm5719-llvm-40feb7f1570ab6f0d05993dc1513a9760a905c4c.tar.gz
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[DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors are less than half of the output vector size.
This will be needed by a future commit to support sign/zero extending from v8i8 to v8i64 which requires a sign/zero_extend_vector_inreg to be created which requires v8i8 to be concatenated upto v64i8 and goes through this code. llvm-svn: 284204
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp14
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2ba23b3850c..da903764e10 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12983,11 +12983,15 @@ SDValue DAGCombiner::createBuildVecShuffle(SDLoc DL, SDNode *N,
// We can't generate a shuffle node with mismatched input and output types.
// Try to make the types match the type of the output.
if (InVT1 != VT || InVT2 != VT) {
- if (InVT1.getSizeInBits() * 2 == VT.getSizeInBits() && InVT1 == InVT2) {
- // If both input vectors are exactly half the size of the output, concat
- // them. If we have only one (non-zero) input, concat it with undef.
- VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, VecIn1,
- VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(InVT1));
+ if ((VT.getSizeInBits() % InVT1.getSizeInBits() == 0) && InVT1 == InVT2) {
+ // If the output vector length is a multiple of both input lengths,
+ // we can concatenate them and pad the rest with undefs.
+ unsigned NumConcats = VT.getSizeInBits() / InVT1.getSizeInBits();
+ assert(NumConcats >= 2 && "Concat needs at least two inputs!");
+ SmallVector<SDValue, 2> ConcatOps(NumConcats, DAG.getUNDEF(InVT1));
+ ConcatOps[0] = VecIn1;
+ ConcatOps[1] = VecIn2 ? VecIn2 : DAG.getUNDEF(InVT1);
+ VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
VecIn2 = SDValue();
} else if (InVT1.getSizeInBits() == VT.getSizeInBits() * 2) {
if (!TLI.isExtractSubvectorCheap(VT, NumElems))
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