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| author | Amara Emerson <aemerson@apple.com> | 2017-10-09 15:15:09 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2017-10-09 15:15:09 +0000 |
| commit | 24ca39ce71e6312672f58d311b6bb6af727f9ca7 (patch) | |
| tree | 92eafa5cc4f54c2eef848c11ce5d311a740a5331 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 8557e2940813f25d017bed66bf03ac55db6381fa (diff) | |
| download | bcm5719-llvm-24ca39ce71e6312672f58d311b6bb6af727f9ca7.tar.gz bcm5719-llvm-24ca39ce71e6312672f58d311b6bb6af727f9ca7.zip | |
[AArch64] Improve codegen for inverted overflow checking intrinsics
E.g. if we have a (xor(overflow-bit), 1) where overflow-bit comes from an
intrinsic like llvm.sadd.with.overflow then we can kill the xor and use the
inverted condition code for the CSEL.
rdar://28495949
Reviewed By: kristof.beyls
Differential Revision: https://reviews.llvm.org/D38160
llvm-svn: 315205
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
0 files changed, 0 insertions, 0 deletions
