diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-11-02 01:47:04 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-11-02 01:47:04 +0000 |
| commit | 17df608719403331f1be3390ab5ed0dd00ec37af (patch) | |
| tree | e533012f59d24a1e51e5e857ab9133a9844eeafa /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 93b8cb17ac9fcf2a8ab83fce9d0640b9c3aba828 (diff) | |
| download | bcm5719-llvm-17df608719403331f1be3390ab5ed0dd00ec37af.tar.gz bcm5719-llvm-17df608719403331f1be3390ab5ed0dd00ec37af.zip | |
Fix a source of undefined behavior when dealing with 64-bit types. This
may fix PR652. Thanks to Andrew for tracking down the problem.
llvm-svn: 24145
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 048737f13e2..b4bd5aa0b42 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -384,7 +384,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::ZERO_EXTEND: SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); - return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); + return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI); case ISD::AssertZext: SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. |
