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authorSimon Pilgrim <llvm-dev@redking.me.uk>2016-09-09 13:31:52 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2016-09-09 13:31:52 +0000
commit153b40843310a00175105908005e3197b837fbc2 (patch)
tree4ccdbe23a78f5bf581e47296b38b1e6831197aa8 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parent08b1862cafc44572f1e75f7a1e0dcd3d73e13e40 (diff)
downloadbcm5719-llvm-153b40843310a00175105908005e3197b837fbc2.tar.gz
bcm5719-llvm-153b40843310a00175105908005e3197b837fbc2.zip
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type
Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f48e1281c7b..249abb998e8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7027,7 +7027,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
- return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
+ return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT.getScalarType());
// fold operands of sext_in_reg based on knowledge that the top bits are not
// demanded.
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