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authorAndrew Lenharth <andrewl@lenharth.org>2006-04-02 21:42:45 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2006-04-02 21:42:45 +0000
commit015eaf5f33898b810848b6af4b496cb4ff578d1c (patch)
treed2d555bc661c70366a2fae9ad622bb73568fd1a3 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parent444bdb069abca004ce91ca469b0b3db84730d7e5 (diff)
downloadbcm5719-llvm-015eaf5f33898b810848b6af4b496cb4ff578d1c.tar.gz
bcm5719-llvm-015eaf5f33898b810848b6af4b496cb4ff578d1c.zip
This should be a win of every arch
llvm-svn: 27364
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp27
1 files changed, 26 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f0003f0d6cd..6bb4ea23a52 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -818,7 +818,32 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) {
DAG.getConstant(Log2_64(-N1C->getSignExtended()),
TLI.getShiftAmountTy())));
}
-
+
+ //These two might be better as:
+ // mul x, ((1 << c) + cn) -> (x << c) + (x * cn)
+ // where TargetInfo tells us cn is a cheap constant to multiply by
+
+ // fold (mul x, (1 << c) + 1) -> (x << c) + x
+ //FIXME: there should be a target hint to allow other constants based on
+ // expense of mul
+ if (N1C && isPowerOf2_64(N1C->getSignExtended() - 1)) {
+ return DAG.getNode(ISD::ADD, VT,
+ DAG.getNode(ISD::SHL, VT, N0,
+ DAG.getConstant(Log2_64(N1C->getSignExtended() - 1),
+ TLI.getShiftAmountTy())),
+ N0);
+ }
+ // fold (mul x, (1 << c) - 1) -> (x << c) - x
+ //FIXME: there should be a target hint to allow other constants based on
+ // the expense of mul
+ if (N1C && isPowerOf2_64(N1C->getSignExtended() + 1)) {
+ return DAG.getNode(ISD::SUB, VT,
+ DAG.getNode(ISD::SHL, VT, N0,
+ DAG.getConstant(Log2_64(N1C->getSignExtended() + 1),
+ TLI.getShiftAmountTy())),
+ N0);
+ }
+
// (mul (shl X, c1), c2) -> (mul X, c2 << c1)
if (N1C && N0.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(N0.getOperand(1))) {
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