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authorMatthias Braun <matze@braunis.de>2015-08-24 22:59:52 +0000
committerMatthias Braun <matze@braunis.de>2015-08-24 22:59:52 +0000
commitb2b7ef1de8118095963e1c085467fc411bd7e56f (patch)
tree10da40c76c37d53e59e8197182bd65cfffde9301 /llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
parent008ff14acf9ce39d855dbeeb622e0598bbad0d93 (diff)
downloadbcm5719-llvm-b2b7ef1de8118095963e1c085467fc411bd7e56f.tar.gz
bcm5719-llvm-b2b7ef1de8118095963e1c085467fc411bd7e56f.zip
MachineBasicBlock: Add liveins() method returning an iterator_range
llvm-svn: 245895
Diffstat (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.cpp')
-rw-r--r--llvm/lib/CodeGen/ScheduleDAGInstrs.cpp14
1 files changed, 5 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 7ce2e0d3beb..3123446fbcc 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -242,11 +242,9 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
assert(Uses.empty() && "Uses in set before adding deps?");
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI)
- for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
- E = (*SI)->livein_end(); I != E; ++I) {
- unsigned Reg = *I;
- if (!Uses.contains(Reg))
- Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
+ for (unsigned LI : (*SI)->liveins()) {
+ if (!Uses.contains(LI))
+ Uses.insert(PhysRegSUOper(&ExitSU, -1, LI));
}
}
}
@@ -1080,11 +1078,9 @@ void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
// Examine the live-in regs of all successors.
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI) {
- for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
- E = (*SI)->livein_end(); I != E; ++I) {
- unsigned Reg = *I;
+ for (unsigned LI : (*SI)->liveins()) {
// Repeat, for reg and all subregs.
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
+ for (MCSubRegIterator SubRegs(LI, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
LiveRegs.set(*SubRegs);
}
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