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authorHiroshi Inoue <inouehrs@jp.ibm.com>2018-01-17 12:29:38 +0000
committerHiroshi Inoue <inouehrs@jp.ibm.com>2018-01-17 12:29:38 +0000
commit8f976ba0bf81a890e4690aa923df2f0f0346ae49 (patch)
tree69e6f2fe27e8823236b1d036bea7a9d32ee8ff37 /llvm/lib/CodeGen/RegisterPressure.cpp
parent3efd1c516c6f85daccb8670b627ecd32091c8d7a (diff)
downloadbcm5719-llvm-8f976ba0bf81a890e4690aa923df2f0f0346ae49.tar.gz
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[NFC] fix trivial typos in comments
"the the" -> "the" llvm-svn: 322636
Diffstat (limited to 'llvm/lib/CodeGen/RegisterPressure.cpp')
-rw-r--r--llvm/lib/CodeGen/RegisterPressure.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 9ac810c7c72..bc1af1594c2 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -587,7 +587,7 @@ void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS,
for (auto I = Defs.begin(); I != Defs.end(); ) {
LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, I->RegUnit,
Pos.getDeadSlot());
- // If the the def is all that is live after the instruction, then in case
+ // If the def is all that is live after the instruction, then in case
// of a subregister def we need a read-undef flag.
unsigned RegUnit = I->RegUnit;
if (TargetRegisterInfo::isVirtualRegister(RegUnit) &&
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