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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-06-24 00:52:22 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-06-24 00:52:22 +0000
commitdbb58d297434d58fbe0d35e691ee147bdd9c09c0 (patch)
treefe6bd78cbc9ac7da68fea136b3519ba426eb8ce4 /llvm/lib/CodeGen/RegisterCoalescer.cpp
parent0f60709f0e860d84522ab77dc07c57b179ee2692 (diff)
downloadbcm5719-llvm-dbb58d297434d58fbe0d35e691ee147bdd9c09c0.tar.gz
bcm5719-llvm-dbb58d297434d58fbe0d35e691ee147bdd9c09c0.zip
Revert "Replace a big gob of old coalescer logic with the new CoalescerPair class."
Whiny buildbots. llvm-svn: 106710
Diffstat (limited to 'llvm/lib/CodeGen/RegisterCoalescer.cpp')
-rw-r--r--llvm/lib/CodeGen/RegisterCoalescer.cpp20
1 files changed, 5 insertions, 15 deletions
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index b943a271b6f..b18f0957b62 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -63,7 +63,7 @@ bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
bool CoalescerPair::setRegisters(const MachineInstr *MI) {
srcReg_ = dstReg_ = subIdx_ = 0;
newRC_ = 0;
- flipped_ = crossClass_ = false;
+ flipped_ = false;
unsigned Src, Dst, SrcSub, DstSub;
if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub))
@@ -78,7 +78,6 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
std::swap(SrcSub, DstSub);
flipped_ = true;
}
- origDstReg_ = Dst;
const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
@@ -101,19 +100,11 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
} else {
// Both registers are virtual.
- // Both registers have subreg indices.
- if (SrcSub && DstSub) {
- // For now we only handle the case of identical indices in commensurate
- // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
- // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
- if (SrcSub != DstSub)
- return false;
- const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
- const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
- if (!getCommonSubClass(DstRC, SrcRC))
- return false;
+ // Identical sub to sub.
+ if (SrcSub == DstSub)
SrcSub = DstSub = 0;
- }
+ else if (SrcSub && DstSub)
+ return false; // FIXME: Qreg:ssub_3 + Dreg:ssub_1 => QReg:dsub_1 + Dreg.
// There can be no SrcSub.
if (SrcSub) {
@@ -133,7 +124,6 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
newRC_ = getCommonSubClass(DstRC, SrcRC);
if (!newRC_)
return false;
- crossClass_ = newRC_ != DstRC || newRC_ != SrcRC;
}
// Check our invariants
assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
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