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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-26 10:57:05 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-26 10:57:05 +0000 |
| commit | 5beaac433dac39034fa85ca6fa785e86d3260ffa (patch) | |
| tree | ffdc60b0dd5062cb40faf73b29b600eab373f4fa /llvm/lib/CodeGen/RegisterClassInfo.cpp | |
| parent | 75aca9409356366a7db618a1febfd26a62fcba93 (diff) | |
| download | bcm5719-llvm-5beaac433dac39034fa85ca6fa785e86d3260ffa.tar.gz bcm5719-llvm-5beaac433dac39034fa85ca6fa785e86d3260ffa.zip | |
[X86][SSE] Use ISD::MULHS for constant vXi16 ISD::SRA lowering (PR38151)
Similar to the existing ISD::SRL constant vector shifts from D49562, this patch adds ISD::SRA support with ISD::MULHS.
As we're dealing with signed values, we have to handle shift by zero and shift by one special cases, so XOP+AVX2/AVX512 splitting/extension is still a better solution - really we should still use ISD::MULHS if one of the special cases are used but for now I've just left a TODO and filtered by isKnownNeverZero.
Differential Revision: https://reviews.llvm.org/D52171
llvm-svn: 343093
Diffstat (limited to 'llvm/lib/CodeGen/RegisterClassInfo.cpp')
0 files changed, 0 insertions, 0 deletions
