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author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-13 21:01:20 +0000 |
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committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-13 21:01:20 +0000 |
commit | 8cdd0215bf004968dffc50c73c9aaa19cee5822c (patch) | |
tree | 83a48d75e47bb8cf4445366cc9561a5f75e34c0e /llvm/lib/CodeGen/RegAllocSimple.cpp | |
parent | ef9d025ebedc5495b17ba41cb6f3d12bf29af022 (diff) | |
download | bcm5719-llvm-8cdd0215bf004968dffc50c73c9aaa19cee5822c.tar.gz bcm5719-llvm-8cdd0215bf004968dffc50c73c9aaa19cee5822c.zip |
Remove getAllocatedRegNum(). Use getReg() instead.
llvm-svn: 11393
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocSimple.cpp')
-rw-r--r-- | llvm/lib/CodeGen/RegAllocSimple.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/RegAllocSimple.cpp b/llvm/lib/CodeGen/RegAllocSimple.cpp index a40ec64077b..e313004ff48 100644 --- a/llvm/lib/CodeGen/RegAllocSimple.cpp +++ b/llvm/lib/CodeGen/RegAllocSimple.cpp @@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { MachineOperand &op = MI->getOperand(i); if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) { - unsigned virtualReg = (unsigned) op.getAllocatedRegNum(); + unsigned virtualReg = (unsigned) op.getReg(); DEBUG(std::cerr << "op: " << op << "\n"); DEBUG(std::cerr << "\t inst[" << i << "]: "; MI->print(std::cerr, *TM)); @@ -187,11 +187,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // must be same register number as the first operand // This maps a = b + c into b += c, and saves b into a's spot assert(MI->getOperand(1).isRegister() && - MI->getOperand(1).getAllocatedRegNum() && + MI->getOperand(1).getReg() && MI->getOperand(1).isUse() && "Two address instruction invalid!"); - physReg = MI->getOperand(1).getAllocatedRegNum(); + physReg = MI->getOperand(1).getReg(); } else { physReg = getFreeReg(virtualReg); } @@ -205,7 +205,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { } MI->SetMachineOperandReg(i, physReg); DEBUG(std::cerr << "virt: " << virtualReg << - ", phys: " << op.getAllocatedRegNum() << "\n"); + ", phys: " << op.getReg() << "\n"); } } RegClassIdx.clear(); |