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| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:05:23 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:05:23 +0000 |
| commit | 7366fa1aa6d69a63e016abe7baec035690797f5a (patch) | |
| tree | 1d91f99165555819bf5175f2b889f1285f966936 /llvm/lib/CodeGen/RegAllocSimple.cpp | |
| parent | 631006ba48ba5c7a4e00f3ced4a3a9d382ba1dad (diff) | |
| download | bcm5719-llvm-7366fa1aa6d69a63e016abe7baec035690797f5a.tar.gz bcm5719-llvm-7366fa1aa6d69a63e016abe7baec035690797f5a.zip | |
(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
llvm-svn: 6341
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocSimple.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocSimple.cpp b/llvm/lib/CodeGen/RegAllocSimple.cpp index 6b95af82fda..31b637496cf 100644 --- a/llvm/lib/CodeGen/RegAllocSimple.cpp +++ b/llvm/lib/CodeGen/RegAllocSimple.cpp @@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // register in any given instruction unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { - if (op.opIsDef()) { + if (op.opIsDefOnly() || op.opIsDefAndUse()) { if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { // must be same register number as the first operand // This maps a = b + c into b += c, and saves b into a's spot |
