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| author | Misha Brukman <brukman+llvm@gmail.com> | 2002-12-13 11:33:22 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2002-12-13 11:33:22 +0000 |
| commit | 35a358d98112b16cbb6e8afc3dc8e1afacf382b0 (patch) | |
| tree | 586eee0a7b5cf7fa75b6eb481a7fece6d0c9d3a9 /llvm/lib/CodeGen/RegAllocSimple.cpp | |
| parent | 0a3704635857844b74e0d5c5d5884b0c62068c36 (diff) | |
| download | bcm5719-llvm-35a358d98112b16cbb6e8afc3dc8e1afacf382b0.tar.gz bcm5719-llvm-35a358d98112b16cbb6e8afc3dc8e1afacf382b0.zip | |
This should be more correct: invalidates physical registers that are used in
an instruction to avoid using them to allocate to other virtual registers.
llvm-svn: 5013
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocSimple.cpp | 45 |
1 files changed, 41 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/RegAllocSimple.cpp b/llvm/lib/CodeGen/RegAllocSimple.cpp index 609eabf5161..3a58b5abeed 100644 --- a/llvm/lib/CodeGen/RegAllocSimple.cpp +++ b/llvm/lib/CodeGen/RegAllocSimple.cpp @@ -79,6 +79,36 @@ namespace { RegClassIdx.clear(); } + /// Invalidates any references, real or implicit, to physical registers + /// + void invalidatePhysRegs(const MachineInstr *MI) { + unsigned Opcode = MI->getOpcode(); + const MachineInstrInfo &MII = TM.getInstrInfo(); + const MachineInstrDescriptor &Desc = MII.get(Opcode); + const unsigned *regs = Desc.ImplicitUses; + while (*regs) + RegsUsed[*regs++] = 1; + + regs = Desc.ImplicitDefs; + while (*regs) + RegsUsed[*regs++] = 1; + + + /* + for (int i = MI->getNumOperands() - 1; i >= 0; --i) { + const MachineOperand &op = MI->getOperand(i); + if (op.isMachineRegister()) + RegsUsed[op.getAllocatedRegNum()] = 1; + } + + for (int i = MI->getNumImplicitRefs() - 1; i >= 0; --i) { + const MachineOperand &op = MI->getImplicitOp(i); + if (op.isMachineRegister()) + RegsUsed[op.getAllocatedRegNum()] = 1; + } + */ + } + void cleanupAfterFunction() { RegMap.clear(); SSA2PhysRegMap.clear(); @@ -222,6 +252,12 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { // get rid of the phi MBB->erase(MBB->begin()); + // a preliminary pass that will invalidate any registers that + // are used by the instruction (including implicit uses) + invalidatePhysRegs(MI); + + DEBUG(std::cerr << "num invalid regs: " << RegsUsed.size() << "\n"); + DEBUG(std::cerr << "num ops: " << MI->getNumOperands() << "\n"); MachineOperand &targetReg = MI->getOperand(0); @@ -285,13 +321,13 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { saveVirtRegToStack(opBlock, opI, virtualReg, opPhysReg); } } + + // make regs available to other instructions + clearAllRegs(); } // really delete the instruction delete MI; - - // make regs available to other instructions - clearAllRegs(); } //loop over each basic block @@ -299,8 +335,9 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { { MachineInstr *MI = *I; - // FIXME: add a preliminary pass that will invalidate any registers that + // a preliminary pass that will invalidate any registers that // are used by the instruction (including implicit uses) + invalidatePhysRegs(MI); // Loop over uses, move from memory into registers for (int i = MI->getNumOperands() - 1; i >= 0; --i) { |

