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| author | Devang Patel <dpatel@apple.com> | 2008-12-23 21:55:04 +0000 |
|---|---|---|
| committer | Devang Patel <dpatel@apple.com> | 2008-12-23 21:55:04 +0000 |
| commit | 323dbe57a6578a6f3456a062878d337cf657a1da (patch) | |
| tree | fa982b20c2c81e20abd11e935679d293c37d27e9 /llvm/lib/CodeGen/RegAllocSimple.cpp | |
| parent | 12f2490489c884cd729ad3ac4f8f5583213b4682 (diff) | |
| download | bcm5719-llvm-323dbe57a6578a6f3456a062878d337cf657a1da.tar.gz bcm5719-llvm-323dbe57a6578a6f3456a062878d337cf657a1da.zip | |
Silience unused warnings.
llvm-svn: 61390
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocSimple.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/RegAllocSimple.cpp b/llvm/lib/CodeGen/RegAllocSimple.cpp index 7dc98904abc..5e5290ce3e3 100644 --- a/llvm/lib/CodeGen/RegAllocSimple.cpp +++ b/llvm/lib/CodeGen/RegAllocSimple.cpp @@ -122,7 +122,9 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg); TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); +#ifndef NDEBUG TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); +#endif while (1) { unsigned regIdx = RegClassIdx[RC]++; |
