summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2008-03-11 07:19:34 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-03-11 07:19:34 +0000
commite88a625ecd110448a5b8c74f2396fea210fc5bdf (patch)
tree398381579f4c290a6c56f3374d2b4737affc319c /llvm/lib/CodeGen/RegAllocLinearScan.cpp
parent5b59e372dcb4776bd2acb4ae0c6438aead9fe7c2 (diff)
downloadbcm5719-llvm-e88a625ecd110448a5b8c74f2396fea210fc5bdf.tar.gz
bcm5719-llvm-e88a625ecd110448a5b8c74f2396fea210fc5bdf.zip
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
llvm-svn: 48218
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocLinearScan.cpp')
-rw-r--r--llvm/lib/CodeGen/RegAllocLinearScan.cpp24
1 files changed, 22 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/RegAllocLinearScan.cpp b/llvm/lib/CodeGen/RegAllocLinearScan.cpp
index d43cc19683c..12e7d6a6975 100644
--- a/llvm/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/llvm/lib/CodeGen/RegAllocLinearScan.cpp
@@ -561,6 +561,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// is very bad (it contains all callee clobbered registers for any functions
// with a call), so we want to avoid doing that if possible.
unsigned physReg = getFreePhysReg(cur);
+ unsigned BestPhysReg = physReg;
if (physReg) {
// We got a register. However, if it's in the fixed_ list, we might
// conflict with it. Check to see if we conflict with it or any of its
@@ -685,8 +686,27 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
}
// All registers must have inf weight. Just grab one!
- if (!minReg)
- minReg = *RC->allocation_order_begin(*mf_);
+ if (!minReg) {
+ if (BestPhysReg)
+ minReg = BestPhysReg;
+ else {
+ // Get the physical register with the fewest conflicts.
+ unsigned MinConflicts = ~0U;
+ for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
+ e = RC->allocation_order_end(*mf_); i != e; ++i) {
+ unsigned reg = *i;
+ unsigned NumConflicts = li_->getNumConflictsWithPhysReg(*cur, reg);
+ if (NumConflicts <= MinConflicts) {
+ MinConflicts = NumConflicts;
+ minReg = reg;
+ }
+ }
+ }
+
+ if (cur->weight == HUGE_VALF || cur->getSize() == 1)
+ // Spill a physical register around defs and uses.
+ li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
+ }
}
DOUT << "\t\tregister with min weight: "
OpenPOWER on IntegriCloud