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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-14 00:58:47 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-14 00:58:47 +0000 |
| commit | eba9095df23cbd844eab6a204f625caa17b7b541 (patch) | |
| tree | ad650c701b792215875553850e44c54769cdfcc6 /llvm/lib/CodeGen/RegAllocGreedy.cpp | |
| parent | 36eab1cee47c8fd2b3ddb872f947c28c1ed666d0 (diff) | |
| download | bcm5719-llvm-eba9095df23cbd844eab6a204f625caa17b7b541.tar.gz bcm5719-llvm-eba9095df23cbd844eab6a204f625caa17b7b541.zip | |
Remove unused vector.
llvm-svn: 121741
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocGreedy.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 402898905e4..943da11ad37 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -273,7 +273,7 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl<LiveInterval*> &SplitVRegs) { // Populate a list of physical register spill candidates. - SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands; + SmallVector<unsigned, 8> PhysRegSpillCands; // Check for an available register in this class. AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs); |
