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authorJakob Stoklund Olesen <stoklund@2pi.dk>2011-05-03 20:42:13 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2011-05-03 20:42:13 +0000
commiteaa6ed1ad81fab3552ed43fef73cf76cb90d5d94 (patch)
tree7f5565f53640996303284816163ace9d268c9e96 /llvm/lib/CodeGen/RegAllocGreedy.cpp
parent3bb2a8153910589eaccb52fb9ae8cbd4237d7f6a (diff)
downloadbcm5719-llvm-eaa6ed1ad81fab3552ed43fef73cf76cb90d5d94.tar.gz
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Gracefully handle invalid live ranges. Fix PR9831.
Register coalescing can sometimes create live ranges that end in the middle of a basic block without any killing instruction. When SplitKit detects this, it will repair the live range by shrinking it to its uses. Live range splitting also needs to know about this. When the range shrinks so much that it becomes allocatable, live range splitting fails because it can't find a good split point. It is paranoid about making progress, so an allocatable range is considered an error. The coalescer should really not be creating these bad live ranges. They appear when coalescing dead copies. llvm-svn: 130787
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocGreedy.cpp')
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 7c461d8ea78..6feb45455d6 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -1315,6 +1315,19 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
SA->analyze(&VirtReg);
+ // FIXME: SplitAnalysis may repair broken live ranges coming from the
+ // coalescer. That may cause the range to become allocatable which means that
+ // tryRegionSplit won't be making progress. This check should be replaced with
+ // an assertion when the coalescer is fixed.
+ if (SA->didRepairRange()) {
+ // VirtReg has changed, so all cached queries are invalid.
+ Order.rewind();
+ while (unsigned PhysReg = Order.next())
+ query(VirtReg, PhysReg).clear();
+ if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
+ return PhysReg;
+ }
+
// First try to split around a region spanning multiple blocks.
unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
if (PhysReg || !NewVRegs.empty())
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