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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-08 23:51:35 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-08 23:51:35 +0000 |
commit | 8c5f0c3115d3066bf35b5e0c2456356d8dbb6c07 (patch) | |
tree | be466577f2f4002baa52a3c853d966599d47c1ba /llvm/lib/CodeGen/RegAllocGreedy.cpp | |
parent | bbedd062c9050a5ddd92398b10d3f9e73adfb1c1 (diff) | |
download | bcm5719-llvm-8c5f0c3115d3066bf35b5e0c2456356d8dbb6c07.tar.gz bcm5719-llvm-8c5f0c3115d3066bf35b5e0c2456356d8dbb6c07.zip |
Properly deal with empty intervals when checking for interference.
llvm-svn: 121319
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocGreedy.cpp')
-rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index c88d474315e..f69979bf2aa 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -173,6 +173,7 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, // Found an available register. return PhysReg; } + assert(!VirtReg.empty() && "Empty VirtReg has interference"); LiveInterval *interferingVirtReg = Queries[interfReg].firstInterference().liveUnionPos().value(); |