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| author | Oliver Stannard <oliver.stannard@arm.com> | 2018-09-27 16:19:04 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2018-09-27 16:19:04 +0000 |
| commit | 2721e6f0ed6690c7978b174f7bac7c9a2e0955e3 (patch) | |
| tree | 7f9ac84e9f2a4df5756a7387c3b128baf2bebb0f /llvm/lib/CodeGen/RegAllocGreedy.cpp | |
| parent | a981f67bcde2f7e0d8c2f1b268c0a156c9e2fef5 (diff) | |
| download | bcm5719-llvm-2721e6f0ed6690c7978b174f7bac7c9a2e0955e3.tar.gz bcm5719-llvm-2721e6f0ed6690c7978b174f7bac7c9a2e0955e3.zip | |
[AArch64] Refactor immediate details out of add/sub tblgen class (NFCI)
Bits [23-22] are used in Add and Sub to specify the shift. The value of the
shift field must be 0x; values of 1x are unallocated. MTE adds some instructions
that use such encodings, and this patch refactors the Add/Sub class so that
another class could derive from this one to implement other encodings and other
formats of bitfields.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52489
llvm-svn: 343231
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocGreedy.cpp')
0 files changed, 0 insertions, 0 deletions
