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| author | John Brawn <john.brawn@arm.com> | 2018-12-14 14:07:57 +0000 |
|---|---|---|
| committer | John Brawn <john.brawn@arm.com> | 2018-12-14 14:07:57 +0000 |
| commit | 1d0d86ae40fbc7b6dfc2b39098c9fe4e47e3a710 (patch) | |
| tree | 1fa176dceaceaad224efd906b8e844007dadb71b /llvm/lib/CodeGen/RegAllocGreedy.cpp | |
| parent | 113e2cd958d7d1e4ea26febade4fb7eada73239f (diff) | |
| download | bcm5719-llvm-1d0d86ae40fbc7b6dfc2b39098c9fe4e47e3a710.tar.gz bcm5719-llvm-1d0d86ae40fbc7b6dfc2b39098c9fe4e47e3a710.zip | |
[RegAllocGreedy] IMPLICIT_DEF values shouldn't prefer registers
It costs nothing to spill an IMPLICIT_DEF value (the only spill code that's
generated is a KILL of the value), so when creating split constraints if the
live-out value is IMPLICIT_DEF the exit constraint should be DontCare instead
of PrefReg.
Differential Revision: https://reviews.llvm.org/D55652
llvm-svn: 349151
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocGreedy.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 64da8485389..f244028534f 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -1183,7 +1183,10 @@ bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf, BC.Number = BI.MBB->getNumber(); Intf.moveToBlock(BC.Number); BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; - BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare; + BC.Exit = (BI.LiveOut && + !LIS->getInstructionFromIndex(BI.LastInstr)->isImplicitDef()) + ? SpillPlacement::PrefReg + : SpillPlacement::DontCare; BC.ChangesValue = BI.FirstDef.isValid(); if (!Intf.hasInterference()) |
