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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-17 02:49:21 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-17 02:49:21 +0000 |
| commit | e07a408afc8a6f1342051c91fefb345960e1ff62 (patch) | |
| tree | be7d96399c86e84f271f01e11559a7e14b7141b9 /llvm/lib/CodeGen/RegAllocFast.cpp | |
| parent | 1069a096916cef8a7c25c8eff2a91f59cc6ff2e8 (diff) | |
| download | bcm5719-llvm-e07a408afc8a6f1342051c91fefb345960e1ff62.tar.gz bcm5719-llvm-e07a408afc8a6f1342051c91fefb345960e1ff62.zip | |
Sprinkle superregister <imp-def> and <imp-kill> operands when dealing with subregister indices.
llvm-svn: 103931
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocFast.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocFast.cpp | 38 |
1 files changed, 28 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 484b36580a0..a6461de55ae 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -151,7 +151,7 @@ namespace { unsigned reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint); void spillAll(MachineInstr *MI); - void setPhysReg(MachineOperand &MO, unsigned PhysReg); + bool setPhysReg(MachineOperand &MO, unsigned PhysReg); }; char RAFast::ID = 0; } @@ -589,12 +589,32 @@ unsigned RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, } // setPhysReg - Change MO the refer the PhysReg, considering subregs. -void RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) { - if (unsigned Idx = MO.getSubReg()) { - MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, Idx) : 0); - MO.setSubReg(0); - } else +// This may invalidate MO if it is necessary to add implicit kills for a +// superregister. +// Return tru if MO kills its register. +bool RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) { + if (!MO.getSubReg()) { MO.setReg(PhysReg); + return MO.isKill() || MO.isDead(); + } + + // Handle subregister index. + MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); + MO.setSubReg(0); + if (MO.isUse()) { + if (MO.isKill()) { + MO.getParent()->addRegisterKilled(PhysReg, TRI, true); + return true; + } + return false; + } + // A subregister def implicitly defines the whole physreg. + if (MO.isDead()) { + MO.getParent()->addRegisterDead(PhysReg, TRI, true); + return true; + } + MO.getParent()->addRegisterDefined(PhysReg, TRI); + return false; } void RAFast::AllocateBasicBlock() { @@ -709,8 +729,7 @@ void RAFast::AllocateBasicBlock() { if (MO.isUse()) { unsigned PhysReg = reloadVirtReg(MI, i, Reg, CopyDst); CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0; - setPhysReg(MO, PhysReg); - if (MO.isKill()) + if (setPhysReg(MO, PhysReg)) VirtKills.push_back(Reg); } else if (MO.isEarlyClobber()) { unsigned PhysReg = defineVirtReg(MI, i, Reg, 0); @@ -761,12 +780,11 @@ void RAFast::AllocateBasicBlock() { continue; } unsigned PhysReg = defineVirtReg(MI, i, Reg, CopySrc); - if (MO.isDead()) { + if (setPhysReg(MO, PhysReg)) { VirtKills.push_back(Reg); CopyDst = 0; // cancel coalescing; } else CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0; - setPhysReg(MO, PhysReg); } // Process virtreg deads. |

