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authorQuentin Colombet <quentin.colombet@gmail.com>2019-05-08 18:30:26 +0000
committerQuentin Colombet <quentin.colombet@gmail.com>2019-05-08 18:30:26 +0000
commit157427245a1993870870629dd36eb978add90570 (patch)
treed2e2b1cd0c23e60c32543998eef2be96b5bd6331 /llvm/lib/CodeGen/RegAllocFast.cpp
parent9820d04dbcbaba1eeab72be2b436a95074e2a952 (diff)
downloadbcm5719-llvm-157427245a1993870870629dd36eb978add90570.tar.gz
bcm5719-llvm-157427245a1993870870629dd36eb978add90570.zip
[RegAllocFast] Scan physcial reg definitions before assigning virtual reg definitions
When assigning the definitions of an instruction we were updating the available registers while walking the definitions. Some of those definitions may be from physical registers and thus, they are not available for other definitions to take, but by the time we see that we may have already assign these registers to another virtual register. Fix that by walking through all the definitions and mark as unavailable the physical register definitions, then do the virtual register assignments. PR41790 llvm-svn: 360278
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocFast.cpp')
-rw-r--r--llvm/lib/CodeGen/RegAllocFast.cpp20
1 files changed, 16 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index c11ae9cce1a..52502a4b821 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1058,6 +1058,20 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
}
// Third scan.
+ // Mark all physreg defs as used before allocating virtreg defs.
+ for (unsigned I = 0; I != DefOpEnd; ++I) {
+ const MachineOperand &MO = MI.getOperand(I);
+ if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
+ continue;
+ unsigned Reg = MO.getReg();
+
+ if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg) ||
+ !MRI->isAllocatable(Reg))
+ continue;
+ definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
+ }
+
+ // Fourth scan.
// Allocate defs and collect dead defs.
for (unsigned I = 0; I != DefOpEnd; ++I) {
const MachineOperand &MO = MI.getOperand(I);
@@ -1065,11 +1079,9 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
continue;
unsigned Reg = MO.getReg();
- if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
- if (!MRI->isAllocatable(Reg)) continue;
- definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
+ // We have already dealt with phys regs in the previous scan.
+ if (TargetRegisterInfo::isPhysicalRegister(Reg))
continue;
- }
MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg);
if (setPhysReg(MI, MI.getOperand(I), PhysReg)) {
VirtDead.push_back(Reg);
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