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authorTom Stellard <thomas.stellard@amd.com>2013-08-14 23:24:32 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-08-14 23:24:32 +0000
commit8e5da413743382ffa2a59c29d4890f57e3546bd6 (patch)
treeb4d5f038d43e343fdd4a51e8bbd2a3b5345d3c2d /llvm/lib/CodeGen/RegAllocBasic.cpp
parentdf94dc391724b0f9d94d8d2045757a320ec4d414 (diff)
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R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. llvm-svn: 188427
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