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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-08-24 13:00:47 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-08-24 13:00:47 +0000 |
| commit | f114820912b8484a9b40429dd58dd829a87d8c58 (patch) | |
| tree | be69ca39d7d8c08ea7eeefffca70969016558f84 /llvm/lib/CodeGen/RegAllocBase.cpp | |
| parent | 7a50c8c2ba58beaa70879d22c628ebd213fcf4ee (diff) | |
| download | bcm5719-llvm-f114820912b8484a9b40429dd58dd829a87d8c58.tar.gz bcm5719-llvm-f114820912b8484a9b40429dd58dd829a87d8c58.zip | |
[mips] Preparatory work for a generic scheduler
Extend instruction definitions from nearly all ISAs to include
appropriate instruction itineraries. Change MIPS16s gp prologue
generation to use real instructions instead of using a pseudo
instruction.
Reviewers: dsanders, vkalintiris
Differential Review: https://reviews.llvm.org/D23548
llvm-svn: 279623
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocBase.cpp')
0 files changed, 0 insertions, 0 deletions
