Change interface of MachineOperand as follows:

    a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

2 files changed, 10 insertions, 12 deletions

diff --git a/llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp b/llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
index 9fd04d2b0e4..380680448d3 100644
--- a/llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
+++ b/llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
@@ -184,7 +184,7 @@ void LiveRangeInfo::constructLiveRanges() {
       // for each operand that is defined by the instruction
       for (MachineInstr::val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI)
-	if (OpI.isDefOnly() || OpI.isDefAndUse()) {     
+	if (OpI.isDef()) {     
 	  const Value *Def = *OpI;
           bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
@@ -203,8 +203,7 @@ void LiveRangeInfo::constructLiveRanges() {
       // iterate over implicit MI operands and create a new LR
       // for each operand that is defined by the instruction
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) 
-	if (MInst->getImplicitOp(i).opIsDefOnly() ||
-            MInst->getImplicitOp(i).opIsDefAndUse()) {     
+	if (MInst->getImplicitOp(i).isDef()) {
 	  const Value *Def = MInst->getImplicitRef(i);
           LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
 
@@ -342,7 +341,7 @@ void LiveRangeInfo::coalesceLRs()
       // iterate over  MI operands to find defs
       for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
             DefE = MI->end(); DefI != DefE; ++DefI) {
-	if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified
+	if (DefI.isDef()) { // this operand is modified
 	  LiveRange *LROfDef = getLiveRangeForValue( *DefI );
 	  RegClass *RCOfDef = LROfDef->getRegClass();
 
diff --git a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 332ae9524cb..a9a5f3d7fe7 100644
--- a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -250,7 +250,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
       // iterate over all MI operands to find defs
       for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI) {
-       	if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
+       	if (OpI.isDef()) // create a new LR since def
 	  addInterference(*OpI, &LVSetAI, isCallInst);
 
 	// Calculate the spill cost of each live range
@@ -269,8 +269,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
       // instr (currently, only calls have this).
       unsigned NumOfImpRefs =  MInst->getNumImplicitRefs();
       for (unsigned z=0; z < NumOfImpRefs; z++) 
-        if (MInst->getImplicitOp(z).opIsDefOnly() ||
-	    MInst->getImplicitOp(z).opIsDefAndUse())
+        if (MInst->getImplicitOp(z).isDef())
 	  addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
 
     } // for all machine instructions in BB
@@ -295,7 +294,7 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
   for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
          ItE = MInst->end(); It1 != ItE; ++It1) {
     const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1); 
-    assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
+    assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
 
     MachineInstr::const_val_op_iterator It2 = It1;
     for (++It2; It2 != ItE; ++It2) {
@@ -645,8 +644,8 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
 	 "Return value of a ret must be handled elsewhere");
 
   MachineOperand& Op = MInst->getOperand(OpNum);
-  bool isDef =  Op.opIsDefOnly();
-  bool isDefAndUse = Op.opIsDefAndUse();
+  bool isDef =  Op.isDef();
+  bool isUse = Op.isUse();
   unsigned RegType = MRI.getRegTypeForLR(LR);
   int SpillOff = LR->getSpillOffFromFP();
   RegClass *RC = LR->getRegClass();
@@ -699,7 +698,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
       assert(scratchReg != MRI.getInvalidRegNum());
     }
   
-  if (!isDef || isDefAndUse) {
+  if (isUse) {
     // for a USE, we have to load the value of LR from stack to a TmpReg
     // and use the TmpReg as one operand of instruction
     
@@ -712,7 +711,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
     AdIMid.clear();
   }
   
-  if (isDef || isDefAndUse) {   // if this is a Def
+  if (isDef) {   // if this is a Def
     // for a DEF, we have to store the value produced by this instruction
     // on the stack position allocated for this LR