Split RegisterAllocation stuff OUT of Sparc.cpp into a well defined pass

that has a very minimal interface (like it should have).

llvm-svn: 1667

1 files changed, 17 insertions, 2 deletions

diff --git a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 61a20198118..6ba63e3051d 100644
--- a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -10,6 +10,7 @@
 //	9/10/01	 -  Ruchira Sasanka - created.
 //**************************************************************************/
 
+#include "llvm/CodeGen/RegisterAllocation.h"
 #include "llvm/CodeGen/PhyRegAlloc.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineCodeForMethod.h"
@@ -23,8 +24,6 @@ using std::cerr;
 // ***TODO: There are several places we add instructions. Validate the order
 //          of adding these instructions.
 
-
-
 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
   "enable register allocation debugging information",
   clEnumValN(RA_DEBUG_None   , "n", "disable debug output"),
@@ -32,6 +31,22 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
   clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
 
 
+bool RegisterAllocation::runOnMethod(Method *M) {
+  if (DEBUG_RA)
+    cerr << "\n******************** Method "<< M->getName()
+         << " ********************\n";
+    
+  MethodLiveVarInfo LVI(M );   // Analyze live varaibles
+  LVI.analyze();
+    
+  PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
+  PRA.allocateRegisters();
+
+  if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
+  return false;
+}
+
+
 //----------------------------------------------------------------------------
 // Constructor: Init local composite objects and create register classes.
 //----------------------------------------------------------------------------