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author | Craig Topper <craig.topper@intel.com> | 2018-03-20 20:53:21 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2018-03-20 20:53:21 +0000 |
commit | 0f110a88bef3b2e46c029c21d9352a120cd995dd (patch) | |
tree | 1a658327d3510a2b45ee3bc5b6844fd9c7584ba4 /llvm/lib/CodeGen/ReachingDefAnalysis.cpp | |
parent | 3f689c86323981117b318c618510f7b4bed909e0 (diff) | |
download | bcm5719-llvm-0f110a88bef3b2e46c029c21d9352a120cd995dd.tar.gz bcm5719-llvm-0f110a88bef3b2e46c029c21d9352a120cd995dd.zip |
[ReachingDefAnalysis] Fix what I assume to be a typo ReachingDedDefaultVal->ReachingDefDefaultVal.
Unless Ded has some many I don't know about.
llvm-svn: 328043
Diffstat (limited to 'llvm/lib/CodeGen/ReachingDefAnalysis.cpp')
-rw-r--r-- | llvm/lib/CodeGen/ReachingDefAnalysis.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp index 6b131b250be..ee76519f885 100644 --- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -34,7 +34,7 @@ void ReachingDefAnalysis::enterBasicBlock( // Set up LiveRegs to represent registers entering MBB. // Default values are 'nothing happened a long time ago'. if (LiveRegs.empty()) - LiveRegs.assign(NumRegUnits, ReachingDedDefaultVal); + LiveRegs.assign(NumRegUnits, ReachingDefDefaultVal); // This is the entry block. if (MBB->pred_empty()) { @@ -64,7 +64,7 @@ void ReachingDefAnalysis::enterBasicBlock( for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) { // Use the most recent predecessor def for each register. LiveRegs[Unit] = std::max(LiveRegs[Unit], Incoming[Unit]); - if ((LiveRegs[Unit] != ReachingDedDefaultVal)) + if ((LiveRegs[Unit] != ReachingDefDefaultVal)) MBBReachingDefs[MBBNumber][Unit].push_back(LiveRegs[Unit]); } } @@ -173,11 +173,11 @@ void ReachingDefAnalysis::releaseMemory() { int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) { assert(InstIds.count(MI) && "Unexpected machine instuction."); int InstId = InstIds[MI]; - int DefRes = ReachingDedDefaultVal; + int DefRes = ReachingDefDefaultVal; unsigned MBBNumber = MI->getParent()->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number."); - int LatestDef = ReachingDedDefaultVal; + int LatestDef = ReachingDefDefaultVal; for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { for (int Def : MBBReachingDefs[MBBNumber][*Unit]) { if (Def >= InstId) |