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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-02-02 18:02:28 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-02-02 18:02:28 +0000 |
| commit | c6b299c8c42199428d2abcb4e977b24e9819c020 (patch) | |
| tree | 678c56643f2cde2ddbc2e591e862a1bfa94895ad /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 4cd6dcd6c431edf48358277ff79c51fbb14c6a93 (diff) | |
| download | bcm5719-llvm-c6b299c8c42199428d2abcb4e977b24e9819c020.tar.gz bcm5719-llvm-c6b299c8c42199428d2abcb4e977b24e9819c020.zip | |
R600/SI: 64-bit and larger memory access must be at least 4-byte aligned
This is true for SI only. CI+ supports unaligned memory accesses,
but this requires driver support, so for now we disallow unaligned
accesses for all GCN targets.
llvm-svn: 227822
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
0 files changed, 0 insertions, 0 deletions
