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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-22 19:16:52 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-22 19:16:52 +0000 |
| commit | 6d05d6a7b62f4b9f42261e5239e2a97d6069344b (patch) | |
| tree | 96c0fce6622aff2c0d051f04e6505c635f87cc85 /llvm/lib/CodeGen/PeepholeOptimizer.cpp | |
| parent | 476e26b5d34dfffa9e6995f1bb8a562d4a2bfa52 (diff) | |
| download | bcm5719-llvm-6d05d6a7b62f4b9f42261e5239e2a97d6069344b.tar.gz bcm5719-llvm-6d05d6a7b62f4b9f42261e5239e2a97d6069344b.zip | |
CodeGen: Make RegAllocRegistry a template class
Will allow re-using the machinery for independent
sets of register allocators.
This will allow AMDGPU to use separate command line
options for the allocator to use for SGPRs separate
from VGPRs.
llvm-svn: 354687
Diffstat (limited to 'llvm/lib/CodeGen/PeepholeOptimizer.cpp')
0 files changed, 0 insertions, 0 deletions
