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author | Kit Barton <kbarton@ca.ibm.com> | 2015-08-14 16:54:32 +0000 |
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committer | Kit Barton <kbarton@ca.ibm.com> | 2015-08-14 16:54:32 +0000 |
commit | ae78d53aebddf837e71ee6714d5d83901dadb72e (patch) | |
tree | 9353f39a19b281fef2d903e311634008d081c805 /llvm/lib/CodeGen/Passes.cpp | |
parent | d7a568fc4ff3553115ca0b33c90f36d925c92f97 (diff) | |
download | bcm5719-llvm-ae78d53aebddf837e71ee6714d5d83901dadb72e.tar.gz bcm5719-llvm-ae78d53aebddf837e71ee6714d5d83901dadb72e.zip |
Reverting patch r244235.
This patch will be redone in a different way. See
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150810/292978.html
for more details.
llvm-svn: 245071
Diffstat (limited to 'llvm/lib/CodeGen/Passes.cpp')
-rw-r--r-- | llvm/lib/CodeGen/Passes.cpp | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/Passes.cpp b/llvm/lib/CodeGen/Passes.cpp index f3a81e8dc0f..4e68cbdd7f5 100644 --- a/llvm/lib/CodeGen/Passes.cpp +++ b/llvm/lib/CodeGen/Passes.cpp @@ -56,6 +56,9 @@ static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM")); static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination")); +static cl::opt<cl::boolOrDefault> + EnableShrinkWrapOpt("enable-shrink-wrap", cl::Hidden, + cl::desc("enable the shrink-wrapping pass")); static cl::opt<cl::boolOrDefault> OptimizeRegAlloc( "optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path.")); @@ -218,7 +221,7 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) : ImmutablePass(ID), PM(&pm), StartBefore(nullptr), StartAfter(nullptr), StopAfter(nullptr), Started(true), Stopped(false), AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false), - DisableVerify(false), EnableTailMerge(true) { + DisableVerify(false), EnableTailMerge(true), EnableShrinkWrap(false) { Impl = new PassConfigImpl(); @@ -540,8 +543,8 @@ void TargetPassConfig::addMachinePasses() { addPostRegAlloc(); // Insert prolog/epilog code. Eliminate abstract frame index references... - if (getOptLevel() != CodeGenOpt::None) - addPass(createShrinkWrapPass()); + if (getEnableShrinkWrap()) + addPass(&ShrinkWrapID); addPass(&PrologEpilogCodeInserterID); /// Add passes that optimize machine instructions after register allocation. @@ -620,6 +623,21 @@ void TargetPassConfig::addMachineSSAOptimization() { addPass(&DeadMachineInstructionElimID); } +bool TargetPassConfig::getEnableShrinkWrap() const { + switch (EnableShrinkWrapOpt) { + case cl::BOU_UNSET: + return EnableShrinkWrap && getOptLevel() != CodeGenOpt::None; + // If EnableShrinkWrap is set, it takes precedence on whatever the + // target sets. The rational is that we assume we want to test + // something related to shrink-wrapping. + case cl::BOU_TRUE: + return true; + case cl::BOU_FALSE: + return false; + } + llvm_unreachable("Invalid shrink-wrapping state"); +} + //===---------------------------------------------------------------------===// /// Register Allocation Pass Configuration //===---------------------------------------------------------------------===// |