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| author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-08-23 05:15:15 +0000 |
|---|---|---|
| committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-08-23 05:15:15 +0000 |
| commit | c4449df1b0ad3a02fe1a90bdeb564897236dc999 (patch) | |
| tree | a98cfd86dafd00033d970f6229f08eec9a3b2f06 /llvm/lib/CodeGen/OptimizePHIs.cpp | |
| parent | 0884b732202d043af4755d05aeb7fd3da8951a24 (diff) | |
| download | bcm5719-llvm-c4449df1b0ad3a02fe1a90bdeb564897236dc999.tar.gz bcm5719-llvm-c4449df1b0ad3a02fe1a90bdeb564897236dc999.zip | |
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate
On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris.
But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR).
This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate.
e.g. (x | 0xFFFFFFFF) should be
ori 3, 3, 65535
oris 3, 3, 65535
but LLVM generates without this patch
li 4, 0
oris 4, 4, 65535
ori 4, 4, 65535
or 3, 3, 4
Differential Revision: https://reviews.llvm.org/D34757
llvm-svn: 311526
Diffstat (limited to 'llvm/lib/CodeGen/OptimizePHIs.cpp')
0 files changed, 0 insertions, 0 deletions
