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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 05:43:46 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 05:43:46 +0000 |
commit | aff10602072d77d974280f98fb6020c5ed70d4b0 (patch) | |
tree | 80a120acb0fdbb41fc0ef51758eea9a5330f60e6 /llvm/lib/CodeGen/MachineVerifier.cpp | |
parent | 7f25c32d5b7b232dbce76d0b57817bc335a54ab1 (diff) | |
download | bcm5719-llvm-aff10602072d77d974280f98fb6020c5ed70d4b0.tar.gz bcm5719-llvm-aff10602072d77d974280f98fb6020c5ed70d4b0.zip |
Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.
llvm-svn: 132455
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index f3478c4790c..471463b46f5 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -744,7 +744,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { RC = SRC; } if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { - if (RC != DRC && !RC->hasSuperClass(DRC)) { + if (!RC->hasSuperClassEq(DRC)) { report("Illegal virtual register for instruction", MO, MONum); *OS << "Expected a " << DRC->getName() << " register, but got a " << RC->getName() << " register\n"; |