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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-08-24 13:37:55 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-08-24 13:37:55 +0000
commita7ed090bba0261162ed1dd018be8a25ec4ba0f81 (patch)
treece58b1afde5d6dbeb5977378877c62c9be41b114 /llvm/lib/CodeGen/MachineVerifier.cpp
parentf114820912b8484a9b40429dd58dd829a87d8c58 (diff)
downloadbcm5719-llvm-a7ed090bba0261162ed1dd018be8a25ec4ba0f81.tar.gz
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Create subranges for new intervals resulting from live interval splitting
The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp15
1 files changed, 11 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 2b38ed36436..d75b90f96a5 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1813,18 +1813,25 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
bool hasRead = false;
bool hasSubRegDef = false;
bool hasDeadDef = false;
+ LaneBitmask RLM = MRI->getMaxLaneMaskForVReg(Reg);
for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
if (!MOI->isReg() || MOI->getReg() != Reg)
continue;
- if (LaneMask != 0 &&
- (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
- continue;
+ unsigned Sub = MOI->getSubReg();
+ LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) : RLM;
if (MOI->isDef()) {
- if (MOI->getSubReg() != 0)
+ if (Sub != 0) {
hasSubRegDef = true;
+ // An operand vreg0:sub0<def> reads vreg0:sub1..n. Invert the lane
+ // mask for subregister defs. Read-undef defs will be handled by
+ // readsReg below.
+ SLM = ~SLM & RLM;
+ }
if (MOI->isDead())
hasDeadDef = true;
}
+ if (LaneMask != 0 && !(LaneMask & SLM))
+ continue;
if (MOI->readsReg())
hasRead = true;
}
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