summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/MachineVerifier.cpp
diff options
context:
space:
mode:
authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-06-25 18:18:27 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-06-25 18:18:27 +0000
commita57fc12ec929c6d762e68f53c0f9ae17be2e2d51 (patch)
tree5d3189b319c915d4e4f3fcdd50ff093c3ae59cea /llvm/lib/CodeGen/MachineVerifier.cpp
parenteb49566447ba2ef4e9be32f32e896e3e1cee0b54 (diff)
downloadbcm5719-llvm-a57fc12ec929c6d762e68f53c0f9ae17be2e2d51.tar.gz
bcm5719-llvm-a57fc12ec929c6d762e68f53c0f9ae17be2e2d51.zip
Enforce stricter liveness rules for PHIs.
Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. llvm-svn: 159150
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp17
1 files changed, 11 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 92d9356e83b..a443b51d15e 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1049,7 +1049,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
// Now check liveness info if available
calcRegsRequired();
- if (MRI->isSSA() && !MF->empty()) {
+ if (!MF->empty()) {
BBInfo &MInfo = MBBInfoMap[&MF->front()];
for (RegSet::iterator
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
@@ -1332,15 +1332,18 @@ void MachineVerifier::verifyLiveIntervals() {
++MFI;
continue;
}
+
+ // Is VNI a PHI-def in the current block?
+ bool IsPHI = VNI->isPHIDef() &&
+ VNI->def == LiveInts->getMBBStartIdx(MFI);
+
// Check that VNI is live-out of all predecessors.
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
PE = MFI->pred_end(); PI != PE; ++PI) {
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
- if (VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI))
- continue;
-
+ // All predecessors must have a live-out value.
if (!PVNI) {
report("Register not marked live out of predecessor", *PI);
*OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
@@ -1349,12 +1352,14 @@ void MachineVerifier::verifyLiveIntervals() {
continue;
}
- if (PVNI != VNI) {
+ // Only PHI-defs can take different predecessor values.
+ if (!IsPHI && PVNI != VNI) {
report("Different value live out of predecessor", *PI);
*OS << "Valno #" << PVNI->id << " live out of BB#"
<< (*PI)->getNumber() << '@' << PEnd
<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
- << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
+ << '@' << LiveInts->getMBBStartIdx(MFI) << " in "
+ << PrintReg(Reg) << ": " << LI << '\n';
}
}
if (&*MFI == EndMBB)
OpenPOWER on IntegriCloud