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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-19 16:10:16 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-19 16:10:16 +0000 |
commit | 267601455eca0399b75181303ce9f34daa634e94 (patch) | |
tree | 2c67e830a520617e0c1d94aa8a029ff1dbafe901 /llvm/lib/CodeGen/MachineVerifier.cpp | |
parent | 2fdd1597153e1d2d7d3161901b4d66d87e500e5e (diff) | |
download | bcm5719-llvm-267601455eca0399b75181303ce9f34daa634e94.tar.gz bcm5719-llvm-267601455eca0399b75181303ce9f34daa634e94.zip |
GlobalISel: Verify g_insert
llvm-svn: 354342
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 99cbe6e653f..4d388708308 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1288,6 +1288,30 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { report("extract reads past end of register", MI); break; } + case TargetOpcode::G_INSERT: { + const MachineOperand &SrcOp = MI->getOperand(2); + if (!SrcOp.isReg()) { + report("insert source must be a register", MI); + break; + } + + const MachineOperand &OffsetOp = MI->getOperand(3); + if (!OffsetOp.isImm()) { + report("insert offset must be a constant", MI); + break; + } + + unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits(); + unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); + + if (DstSize <= SrcSize) + report("inserted size must be smaller than total register", MI); + + if (SrcSize + OffsetOp.getImm() > DstSize) + report("insert writes past end of register", MI); + + break; + } default: break; } |