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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-28 16:46:02 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-28 16:46:02 +0000 |
| commit | 24e80b8d042a1bcf8a3dd6aeb6275c697f83c659 (patch) | |
| tree | 6d0e4daddb3924d03d3a695d49dc8374db883532 /llvm/lib/CodeGen/MachineVerifier.cpp | |
| parent | 7166843f1e10efbdd3a24fccb15ad33bfb6f0f70 (diff) | |
| download | bcm5719-llvm-24e80b8d042a1bcf8a3dd6aeb6275c697f83c659.tar.gz bcm5719-llvm-24e80b8d042a1bcf8a3dd6aeb6275c697f83c659.zip | |
AMDGPU: Don't enable all lanes with non-CSR VGPR spills
If the only VGPRs used for SGPR spilling were not CSRs, this was
enabling all laness and immediately restoring exec. This is the usual
situation in leaf functions.
llvm-svn: 361848
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
0 files changed, 0 insertions, 0 deletions
