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authorCraig Topper <craig.topper@intel.com>2018-04-08 17:53:18 +0000
committerCraig Topper <craig.topper@intel.com>2018-04-08 17:53:18 +0000
commitb7baa358f632324f593deeba3daa3268795bd258 (patch)
treec29b630419f422bb26d81126670d2e2acd405d94 /llvm/lib/CodeGen/MachineTraceMetrics.cpp
parentc362f42b6acc8f159ac7453f370cf72a672cbc12 (diff)
downloadbcm5719-llvm-b7baa358f632324f593deeba3daa3268795bd258.tar.gz
bcm5719-llvm-b7baa358f632324f593deeba3daa3268795bd258.zip
[X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs.
Summary: Cmov and setcc previously used WriteALU, but on Intel processors at least they are more restricted than basic ALU ops. This patch adds new SchedWrites for them and removes the InstRWs. I had to leave some InstRWs for CMOVA/CMOVBE and SETA/SETBE because those have an extra uop relative to the other condition codes on Intel CPUs. The test changes are due to fixing a missing ZnAGU dependency on the memory form of setcc. Reviewers: RKSimon, andreadb, GGanesh Reviewed By: RKSimon Subscribers: GGanesh, llvm-commits Differential Revision: https://reviews.llvm.org/D45380 llvm-svn: 329539
Diffstat (limited to 'llvm/lib/CodeGen/MachineTraceMetrics.cpp')
0 files changed, 0 insertions, 0 deletions
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