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authorYonghong Song <yhs@fb.com>2020-04-19 15:19:06 -0700
committerTom Stellard <tstellar@redhat.com>2020-05-06 19:53:49 -0700
commit1d1469ab64294a6a18410310e0f77f590ee4ba7c (patch)
tree93e3d495c8034af6c111945a086ead344a3178b5 /llvm/lib/CodeGen/MachineSink.cpp
parent98f9f73f6d2367aa8001c4d16de9d3b347febb08 (diff)
downloadbcm5719-llvm-1d1469ab64294a6a18410310e0f77f590ee4ba7c.tar.gz
bcm5719-llvm-1d1469ab64294a6a18410310e0f77f590ee4ba7c.zip
BPF: fix a CORE optimization bug
For the test case in this patch like below struct t { int a; } __attribute__((preserve_access_index)); int foo(void *); int test(struct t *arg) { long param[1]; param[0] = (long)&arg->a; return foo(param); } The IR right before BPF SimplifyPatchable phase: %1:gpr = LD_imm64 @"llvm.t:0:0$0:0" %2:gpr = LDD killed %1:gpr, 0 %3:gpr = ADD_rr %0:gpr(tied-def 0), killed %2:gpr STD killed %3:gpr, %stack.0.param, 0 After SimplifyPatchable phase, the incorrect IR is generated: %1:gpr = LD_imm64 @"llvm.t:0:0$0:0" %3:gpr = ADD_rr %0:gpr(tied-def 0), killed %1:gpr CORE_MEM killed %3:gpr, 306, %0:gpr, @"llvm.t:0:0$0:0" Note that CORE_MEM pseudo op is introduced to encode memory operations related to CORE. In the above, we intend to check whether we have a store like *(%3:gpr + 0) = ... and if this is the case, we could replace it with *(%0:gpr + @"llvm.t:0:0$0:0"_ = ... Unfortunately, in the above, IR for the store is *(%stack.0.param + 0) = %3:gpr and transformation should not happen. Note that we won't have problem if the actual CORE dereference (arg->a) happens. This patch fixed the problem by skip CORE optimization if the use of ADD_rr result is not the base address of the store operation. Differential Revision: https://reviews.llvm.org/D78466 (cherry picked from commit 3cb7e7bf959dcd3b8080986c62e10a75c7af43f0)
Diffstat (limited to 'llvm/lib/CodeGen/MachineSink.cpp')
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