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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 19:57:45 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 19:57:45 +0000 |
| commit | 982224cfb8de39337e977219b3571c5a87aca4ce (patch) | |
| tree | bab1498538efc732c8ef02877d6e289e7729e7e4 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | b7692bc3e9ad2691fc07261904b88fb15f30696b (diff) | |
| download | bcm5719-llvm-982224cfb8de39337e977219b3571c5a87aca4ce.tar.gz bcm5719-llvm-982224cfb8de39337e977219b3571c5a87aca4ce.zip | |
DAGCombiner: Don't unnecessarily swap operands in ReassociateOps
In the case where op = add, y = base_ptr, and x = offset, this
transform:
(op y, (op x, c1)) -> (op (op x, y), c1)
breaks the canonical form of add by putting the base pointer in the
second operand and the offset in the first.
This fix is important for the R600 target, because for some address
spaces the base pointer and the offset are stored in separate register
classes. The old pattern caused the ISel code for matching addressing
modes to put the base pointer and offset in the wrong register classes,
which required no-trivial code transformations to fix.
llvm-svn: 262148
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
0 files changed, 0 insertions, 0 deletions
