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authorChad Rosier <mcrosier@codeaurora.org>2016-01-20 23:08:32 +0000
committerChad Rosier <mcrosier@codeaurora.org>2016-01-20 23:08:32 +0000
commit816a1ab9d9f3f640200895215a19772db11e9c99 (patch)
tree66c14c2574714b372bbff6fc95d7694284a940f9 /llvm/lib/CodeGen/MachineScheduler.cpp
parent6338d7c3904739e9da222cfe748c2fad1ae5af05 (diff)
downloadbcm5719-llvm-816a1ab9d9f3f640200895215a19772db11e9c99.tar.gz
bcm5719-llvm-816a1ab9d9f3f640200895215a19772db11e9c99.zip
MachineScheduler: Add a command line option to disable post scheduler.
llvm-svn: 258364
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 81651aadcfd..a0a10ca276c 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -219,6 +219,11 @@ static cl::opt<bool> EnableMachineSched(
cl::desc("Enable the machine instruction scheduling pass."), cl::init(true),
cl::Hidden);
+static cl::opt<bool> EnablePostRAMachineSched(
+ "enable-post-misched",
+ cl::desc("Enable the post-ra machine instruction scheduling pass."),
+ cl::init(true), cl::Hidden);
+
/// Forward declare the standard machine scheduler. This will be used as the
/// default scheduler if the target does not set a default.
static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C);
@@ -355,7 +360,10 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
if (skipOptnoneFunction(*mf.getFunction()))
return false;
- if (!mf.getSubtarget().enablePostRAScheduler()) {
+ if (EnablePostRAMachineSched.getNumOccurrences()) {
+ if (!EnablePostRAMachineSched)
+ return false;
+ } else if (!mf.getSubtarget().enablePostRAScheduler()) {
DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
return false;
}
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