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authorChangpeng Fang <changpeng.fang@gmail.com>2019-09-26 22:53:44 +0000
committerChangpeng Fang <changpeng.fang@gmail.com>2019-09-26 22:53:44 +0000
commitf5524f04512d1e9b9581fa6b2be4cc0d4bae7450 (patch)
tree6252db0f3eec11890d88b06ca12c7814568c6354 /llvm/lib/CodeGen/MachinePipeliner.cpp
parent945249b5a99d44f494e084a7c1ac5da810f16f6a (diff)
downloadbcm5719-llvm-f5524f04512d1e9b9581fa6b2be4cc0d4bae7450.tar.gz
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Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjoint
Reviewers: arsenm Differential Revision: https://reviews.llvm.org/D58360 llvm-svn: 373024
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index b3d97c61fda..9591211fd9e 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -700,7 +700,7 @@ void SwingSchedulerDAG::addLoopCarriedDependences(AliasAnalysis *AA) {
TII->getMemOperandWithOffset(MI, BaseOp2, Offset2, TRI)) {
if (BaseOp1->isIdenticalTo(*BaseOp2) &&
(int)Offset1 < (int)Offset2) {
- assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI, AA) &&
+ assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI) &&
"What happened to the chain edge?");
SDep Dep(Load, SDep::Barrier);
Dep.setLatency(1);
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