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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-04-07 12:10:11 +0000 |
|---|---|---|
| committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-04-07 12:10:11 +0000 |
| commit | 3d5ce49ce5c968aa4b321843f37cdcb4eecdf834 (patch) | |
| tree | 222b1e296de147b17d2e22f551984394546ea5a0 /llvm/lib/CodeGen/MachineModuleInfoImpls.cpp | |
| parent | 14ed198ff719bf851c10434500ec88740ffca30c (diff) | |
| download | bcm5719-llvm-3d5ce49ce5c968aa4b321843f37cdcb4eecdf834.tar.gz bcm5719-llvm-3d5ce49ce5c968aa4b321843f37cdcb4eecdf834.zip | |
[TableGen] Prevent invalid code generation when emitting AssemblerPredicate conditions.
Summary:
The loop which emits AssemblerPredicate conditions also links them together by emitting a '&&'.
If the 1st predicate is not an AssemblerPredicate, while the 2nd one is, nothing gets emitted for the 1st one, but we still emit the '&&' because of the 2nd predicate.
This generated code looks like "( && Cond2)" and is invalid.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D8294
llvm-svn: 234312
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp')
0 files changed, 0 insertions, 0 deletions
