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| author | Elad Cohen <elad2.cohen@intel.com> | 2017-08-10 07:44:23 +0000 |
|---|---|---|
| committer | Elad Cohen <elad2.cohen@intel.com> | 2017-08-10 07:44:23 +0000 |
| commit | 22ba97a0a6be75d2d5d497152da3782bd9270ba2 (patch) | |
| tree | 8a13be6830be196e02484668794ed82e12f089e0 /llvm/lib/CodeGen/MachineLICM.cpp | |
| parent | f43e7c2e9733448624fe05cd186cc440daf83e4b (diff) | |
| download | bcm5719-llvm-22ba97a0a6be75d2d5d497152da3782bd9270ba2.tar.gz bcm5719-llvm-22ba97a0a6be75d2d5d497152da3782bd9270ba2.zip | |
[SelectionDAG] When scalarizing vselect, don't assert on
a legal cond operand.
When scalarizing the result of a vselect, the legalizer currently expects
to already have scalarized the operands. While this is true for the true/false
operands (which have the same type as the result), it is not case for the
condition operand. On X86 AVX512, v1i1 is legal - this leads to operations such
as '< N x type> vselect < N x i1> < N x type> < N x type>' where < N x type > is
illegal to hit an assertion during the scalarization.
The handling is similar to r205625.
This also exposes the fact that (v1i1 extract_subvector) should be legal
and selectable on AVX512 - We do this by custom lowering to vector_extract_elt.
This still leaves us in some cases with redundant dag nodes which will be
combined in a separate soon to come patch.
This fixes pr33349.
Differential revision: https://reviews.llvm.org/D36511
llvm-svn: 310552
Diffstat (limited to 'llvm/lib/CodeGen/MachineLICM.cpp')
0 files changed, 0 insertions, 0 deletions
