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| author | Nikolay Haustov <Nikolay.Haustov@amd.com> | 2016-02-25 16:09:14 +0000 |
|---|---|---|
| committer | Nikolay Haustov <Nikolay.Haustov@amd.com> | 2016-02-25 16:09:14 +0000 |
| commit | 161a158e5c497a54ea0ba588d242fa98e7c0a3e8 (patch) | |
| tree | a5aa3416c4e73a31d7908e074783989384e55452 /llvm/lib/CodeGen/MachineFunctionPass.cpp | |
| parent | 26df21d71ecc37a57a532df4a71a33acca8e0a88 (diff) | |
| download | bcm5719-llvm-161a158e5c497a54ea0ba588d242fa98e7c0a3e8.tar.gz bcm5719-llvm-161a158e5c497a54ea0ba588d242fa98e7c0a3e8.zip | |
[AMDGPU] Disassembler: Support for all VOP1 instructions.
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget:
VGPR_32 and VReg_64 operand register classes
VS_32 and VS_64 operand register classes with inline and literal constants
Tests for VOP1 instructions.
Patch by: skolton
Reviewers: arsenm, tstellarAMD
Review: http://reviews.llvm.org/D17194
llvm-svn: 261878
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunctionPass.cpp')
0 files changed, 0 insertions, 0 deletions
