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authorQuentin Colombet <qcolombet@apple.com>2013-12-12 00:15:47 +0000
committerQuentin Colombet <qcolombet@apple.com>2013-12-12 00:15:47 +0000
commit18b779e3f4c42cda3e77f16109f163f2352029c1 (patch)
tree9d6bd411e2f3faf3c1e02cdfa7e360f4da607730 /llvm/lib/CodeGen/MachineFunction.cpp
parent6f4f77b7e932f911f2c9783f48fa68f854887432 (diff)
downloadbcm5719-llvm-18b779e3f4c42cda3e77f16109f163f2352029c1.tar.gz
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Fix an over-constrained assertion in MachineFunction::addLiveIn.
The assertion was checking that the virtual register VReg used to represent the physical register PReg uses the same register class as the one passed to MachineFunction::addLiveIn. This is over-constraining because it is sufficient to check that the register class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and that VRegRC contains PReg. Indeed, if VReg gets constrained because of some operation constraints between two calls of MachineFunction::addLiveIn, the original assertion cannot match. This fixes <rdar://problem/15633429>. llvm-svn: 197097
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineFunction.cpp11
1 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 0703df09a60..96a5ccb9691 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -425,7 +425,16 @@ unsigned MachineFunction::addLiveIn(unsigned PReg,
MachineRegisterInfo &MRI = getRegInfo();
unsigned VReg = MRI.getLiveInVirtReg(PReg);
if (VReg) {
- assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
+ const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
+ (void)VRegRC;
+ // A physical register can be added several times.
+ // Between two calls, the register class of the related virtual register
+ // may have been constrained to match some operation constraints.
+ // In that case, check that the current register class includes the
+ // physical register and is a sub class of the specified RC.
+ assert((VRegRC == RC || (VRegRC->contains(PReg) &&
+ RC->hasSubClassEq(VRegRC))) &&
+ "Register class mismatch!");
return VReg;
}
VReg = MRI.createVirtualRegister(RC);
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