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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-17 21:43:12 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-17 21:43:12 +0000 |
| commit | c302b9b5fe0e6a1e64f7dde40329904a5bdc29f0 (patch) | |
| tree | b4991710333a10869ae2a97345de9d482d75a9c1 /llvm/lib/CodeGen/MachineDominanceFrontier.cpp | |
| parent | baa94ef03bccbaf7d973c340d873abdaa4e36479 (diff) | |
| download | bcm5719-llvm-c302b9b5fe0e6a1e64f7dde40329904a5bdc29f0.tar.gz bcm5719-llvm-c302b9b5fe0e6a1e64f7dde40329904a5bdc29f0.zip | |
[CodeGen] Prepare for introduction of v3 and v5 MVTs
AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, but makes preparatory changes:
* Exclude non-legal non-power-of-2 vector types from ComputeRegisterProp
mechanism in TargetLoweringBase::getTypeConversion.
* Cope with SETCC and VSELECT for odd-width i1 vector when the other
vectors are legal type.
Some of this patch is from Matt Arsenault, also of AMD.
Differential Revision: https://reviews.llvm.org/D58899
Change-Id: Ib5f23377dbef511be3a936211a0b9f94e46331f8
llvm-svn: 356350
Diffstat (limited to 'llvm/lib/CodeGen/MachineDominanceFrontier.cpp')
0 files changed, 0 insertions, 0 deletions
