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| author | Craig Topper <craig.topper@intel.com> | 2019-06-05 18:25:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-06-05 18:25:09 +0000 |
| commit | d0fff89b81650e1b7d6c9c73c035672099b0c2db (patch) | |
| tree | 45c5037279072f7f6b6a0137284f8bcaa67dcf4b /llvm/lib/CodeGen/MachineCopyPropagation.cpp | |
| parent | 13dd125043fa40b2bf1f8b5d3143b20caf6c68c2 (diff) | |
| download | bcm5719-llvm-d0fff89b81650e1b7d6c9c73c035672099b0c2db.tar.gz bcm5719-llvm-d0fff89b81650e1b7d6c9c73c035672099b0c2db.zip | |
[X86] Add the vector integer min/max instructions to isAssociativeAndCommutative.
As far as I know these should be freely reassociatable just like
the floating point MAXC/MINC instructions.
The *reduce* test changes are largely regressions and caused by
the "generic" CPU we default to not having a scheduler model.
The machine-combiner-int-vec.ll test shows the positive benefits
of this change.
Differential Revision: https://reviews.llvm.org/D62787
llvm-svn: 362629
Diffstat (limited to 'llvm/lib/CodeGen/MachineCopyPropagation.cpp')
0 files changed, 0 insertions, 0 deletions
