summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/MachineCSE.cpp
diff options
context:
space:
mode:
authorOliver Stannard <oliver.stannard@arm.com>2018-10-08 09:18:48 +0000
committerOliver Stannard <oliver.stannard@arm.com>2018-10-08 09:18:48 +0000
commit9ecdac8ee0884b02e3aff87bf61472c207824ef4 (patch)
tree80da4bb78b14e153e762063472140cf4addbaa7b /llvm/lib/CodeGen/MachineCSE.cpp
parent5af6c1496aaf95108af8a928156da503fccb10c9 (diff)
downloadbcm5719-llvm-9ecdac8ee0884b02e3aff87bf61472c207824ef4.tar.gz
bcm5719-llvm-9ecdac8ee0884b02e3aff87bf61472c207824ef4.zip
[AArch64] Fix verifier error when outlining indirect calls
The MachineOutliner for AArch64 transforms indirect calls into indirect tail calls, replacing the call with the TCRETURNri pseudo-instruction. This pseudo lowers to a BR, but has the isCall and isReturn flags set. The problem is that TCRETURNri takes a tcGPR64 as the register argument, to prevent indiret tail-calls from using caller-saved registers. The indirect calls transformed by the outliner could use caller-saved registers. This is fine, because the outliner ensures that the register is available at all call sites. However, this causes a verifier failure when the register is not in tcGPR64. The fix is to add a new pseudo-instruction like TCRETURNri, but which accepts any GPR. Differential revision: https://reviews.llvm.org/D52829 llvm-svn: 343959
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
0 files changed, 0 insertions, 0 deletions
OpenPOWER on IntegriCloud