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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-03-09 03:56:06 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-03-09 03:56:06 +0000 |
| commit | 7c699f92cd54a82d5abe7cb9db1d2d24c56f2690 (patch) | |
| tree | 1416b971d2a016715654ae13c57ca73ee62debe3 /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | 19e44b4510c565433ba0e74a4312b52000b90ade (diff) | |
| download | bcm5719-llvm-7c699f92cd54a82d5abe7cb9db1d2d24c56f2690.tar.gz bcm5719-llvm-7c699f92cd54a82d5abe7cb9db1d2d24c56f2690.zip | |
Don't do illegal cross-class coalescing.
llvm-svn: 98044
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineCSE.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index ada95cd6da5..68407c88d8e 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -95,7 +95,7 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI, !SrcSubIdx && !DstSubIdx) { const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); const TargetRegisterClass *RC = MRI->getRegClass(Reg); - if (SRC == RC || SRC->hasSubClass(RC) || RC->hasSubClass(SRC)) { + if (SRC == RC || RC->hasSubClass(SRC)) { DEBUG(dbgs() << "Coalescing: " << *DefMI); DEBUG(dbgs() << "*** to: " << *MI); MO.setReg(SrcReg); |
